`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:43:25 07/24/2013 
// Design Name: 
// Module Name:    pmap2sel 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module pmap2sel(
    rst_n,
    clk,
    set,
    pmap_in,
    next,
    sel0,
    sel1
    );
    
    input rst_n;
    input clk;
    input set;
    input [49:0] pmap_in;
    input [1:0] next;
    
    output [49:0] sel0;
    output [49:0] sel1;
    
    reg [49:0] sel0;
    reg [49:0] sel1;
    reg [49:0] sel0_next;
    reg [49:0] sel1_next;
    
    reg [49:0] pmap;
    reg [49:0] pmap_next;
    wire [49:0] pmap_n1;
    wire [49:0] pmap_n2;
    
    always @(negedge rst_n, posedge clk)
    begin
        if(~rst_n)
        begin
            pmap <= 50'b0;
            sel0 <= 50'b0;
            sel1 <= 50'b0;
        end
        else
        begin
            pmap <= pmap_next;
            sel0 <= sel0_next;
            sel1 <= sel1_next;
        end
    end

    always @(*)
    begin
        if(set)
        begin
            pmap_next = pmap_in;
            sel0_next = pmap_in & ((~pmap_in) + 1);
            sel1_next = (pmap_in ^ sel0_next) & ((~(pmap_in ^ sel0_next)) + 1 );
        end
        
        else
        begin
            case(next)
                2'd1:
                begin
                    pmap_next = pmap_n1;
                    sel0_next = sel1;
                    sel1_next = pmap_n2 & ((~pmap_n2) + 1);
                end
                2'd2:
                begin
                    pmap_next = pmap_n2;
                    sel0_next = pmap_n2 & ((~pmap_n2) + 1);
                    sel1_next = (pmap_n2 ^ sel0_next) & ((~(pmap_n2 ^ sel0_next)) + 1 );
                end
                default:
                begin
                    pmap_next = pmap;
                    sel0_next = sel0;
                    sel1_next = sel1;
                end
            endcase
        end
    end
    
    assign pmap_n1 = pmap ^ sel0;
    assign pmap_n2 = pmap_n1 ^ sel1;

endmodule
